library ieee;
library altera;
use altera.maxplus2.all;
use ieee.std_logic_1164.all;

package pack is

  type matriz is array (63 downto 0) of std_logic_vector(47 downto 0);  -- matriz
                                        -- de 128x96.
  type estado_t_nosso is (inicializaEst, entradaEst, executaEst, contaVizinhosEst, aplicaRegrasEst);

  component div_freq is
    port (clk, resetn : in     std_logic;
          divisao     : in     std_logic_vector (1 downto 0);
          clk_out     : buffer std_logic);
  end component div_freq;

  component cell is
    port (col            : in  integer range 0 to 95;
          line           : in  integer range 0 to 127;
          tela           :     matriz;
          cor, pixel_bit : out std_logic);
  end component cell;

  component life is
    port (
      masterClock, resetn : in  std_logic;
      div                 : in  std_logic_vector (1 downto 0);
      padroes             : in  std_logic_vector (7 downto 0);
      --iterations                                                          : out integer;
      gameOut             : out matriz);
  end component;

  component conv_7seg is
    port (digit : in  std_logic_vector (3 downto 0);
          seg   : out std_logic_vector (6 downto 0));
  end component conv_7seg;


end pack;
